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quad channel, 16-bit, serial input, 4 ma to 20 ma output dac, dynamic power control, hart connectivity data sheet AD5757 rev. d document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2011C2012 analog devices, inc. all rights reserved. technical support www.analog.com features 16-bit resolution and monotonicity dynamic power control for thermal management or external pmos mode current output ranges: 0 ma to 20 ma, 4 ma to 20 ma, or 0 ma to 24 ma 0.05% total unadjusted error (tue) maximum user programmable offset and gain on-chip diagnostics on-chip reference (10 ppm/c maximum) ?40c to +105c temperature range applications process control actuator control plcs hart network connectivity general description the AD5757 is a quad, current output dac that operates with a power supply range from 10.8 v to 33 v. on-chip dynamic power control minimizes package power dissipation by regulat- ing the voltage on the output driver from 7.4 v to 29.5 v using a dc-to-dc boost converter optimized for minimum on-chip power dissipation. each channel has a corresponding chart pin so that hart signals can be coupled onto the current output of the AD5757. the part uses a versatile 3-wire serial interface that operates at clock rates of up to 30 mhz and is compatible with standard spi, qspi?, microwire?, dsp, and microcontroller interface standards. the interface also features optional crc-8 packet error checking, as well as a watchdog timer that monitors activity on the interface. product highlights 1. dynamic power control for thermal management. 2. 16-bit performance. 3. multichannel. 4. hart compliant. companion products product family: ad5755-1 , ad5755 hart modem: ad5700 , ad5700-1 external references: adr445 , adr02 digital isolators: adum1410 , adum1411 power: adp2302 , adp2303 additional companion products on the AD5757 product page functional block diagram AD5757 agnd av dd +15v a v cc 5.0v dv dd dgnd ldac clear sclk sdin sync sdo fault dc-to-dc converter digital interface reference current and voltage output range scaling alert refout refin notes 1. x = a, b, c, and d. ad1 ad0 dac a sw x v boost_x gain reg a offset reg a r set_x chartx i out_x dac channel b dac channel a dac channel c dac channel d 7.4v to 29.5v + 09225-101 figure 1.
AD5757 data sheet rev. d | page 2 of 44 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 product highlights ........................................................................... 1 companion products ....................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 3 detailed functional block diagram .............................................. 4 specifications ..................................................................................... 5 ac performance characteristics ................................................ 7 timing characteristics ................................................................ 7 absolute maximum ratings .......................................................... 10 esd caution ................................................................................ 10 pin configuration and function descriptions ........................... 11 typical performance characteristics ........................................... 14 current outputs ......................................................................... 14 dc - to - d c block ......................................................................... 1 9 reference ..................................................................................... 20 general ......................................................................................... 21 terminology .................................................................................... 22 theory of operation ...................................................................... 23 dac architecture ....................................................................... 23 power - on state of the AD5757 ................................................ 23 serial interface ............................................................................ 23 transfer function ....................................................................... 24 registers ........................................................................................... 25 programming sequence to write/enable the output correctly ...................................................................................... 26 changing and reprogramming the range ............................. 26 data registers ............................................................................. 27 control registers ........................................................................ 29 readback operation .................................................................. 32 device features ............................................................................... 34 output fault ................................................................................ 34 digital offset and gain control ............................................... 34 status readback during a write .............................................. 34 asynchronous clear ................................................................... 34 packet error checking ............................................................... 34 watchdog timer ......................................................................... 35 output alert ................................................................................ 35 internal reference ...................................................................... 35 external current setting resistor ............................................ 35 hart ........................................................................................... 35 digital slew rate control .......................................................... 36 power dissipation control ........................................................ 36 dc - to - dc converters ............................................................... 36 ai cc supply requirements stati c .......................................... 38 ai cc supply requirements slewing ...................................... 38 external pmos mode ................................................................ 39 a pplications information .............................................................. 40 current output mode with internal r set ................................ 40 precision voltage reference selection ..................................... 40 driving inductive loads ............................................................ 40 transient voltage protection .................................................... 41 microprocessor interfac ing ....................................................... 41 layout guidelines ....................................................................... 41 galvanically isolated interface ................................................. 42 i ndustrial hart capable analog output application .................................................................................. 43 outline dimensions ....................................................................... 44 ordering guide .......................................................................... 44
data sheet AD5757 rev. d | page 3 of 44 revision history 11/12rev. c to rev. d changed thermal impedance from 20c/w to 28c/w .......... 10 changes to pin 6 description ........................................................ 11 changes to dut_ad1, dut_ad0 description, table 8 ......... 27 changes to changes to packet error checking section and internal reference section ............................................................. 35 changes to figure 57 ...................................................................... 37 changes to figure 63 ...................................................................... 41 changes to figure 66 ...................................................................... 43 updated outline dimensions ........................................................ 44 5/12rev. b to rev. c changes to companion products section ..................................... 1 changes to table 5 .......................................................................... 13 added industrial hart capable analog output application section and figure 66, renumbered sequentially ...................... 43 updated outline dimensions ........................................................ 44 11/11rev. a to rev. b change to test conditions/comments of accuracy (external r set ) parameter, table 1 .................................................................... 5 changes to figure 4 ........................................................................... 8 changes to figure 5 ........................................................................... 9 change to pin 8 description, table 5 ........................................... 11 change to figure 13 ........................................................................ 14 change to figure 20 ........................................................................ 16 changes to figure 48 and power-on state of the AD5757 section .............................................................................................. 23 change to table 16 .......................................................................... 29 changes to readback operation section, readback example section, and table 25 ...................................................................... 32 change to figure 54 ........................................................................ 35 change to figure 58 caption ......................................................... 38 changes to figure 59, figure 60, and figure 61 captions ......... 39 changes to transient voltage protection section and figure 63 ........................................................................................... 41 changes to galvanically isolated interface section .................... 42 5/11rev. 0 to rev. a changes features section ................................................................. 1 changes to figure 2 .......................................................................... 3 changed av dd min parameter from 10.8 v to 9 v ...................... 5 changes to pin 22, pin31, pin 49 descriptions ........................... 11 changes to pin 58 descriptions .................................................... 12 changes to figure 8, figure 9, and figure 10 .............................. 13 added figure 23, renumbered sequentially ............................... 15 added figure 29 .............................................................................. 16 added external pmos mode section and figure 62 ................. 38 4/11revision 0: initial version
AD5757 data sheet rev. d | page 4 of 44 detailed functional block diagram AD5757 agnd av dd +15v av cc 5.0v dv dd dgnd ldac clear sclk sdin sync sdo fault dc-to-dc converter power control input shift register and control status register power-on reset reference buffers dac reg a input reg a vref watchdog timer (spi activity) alert refout refin ad1 ad0 dac a 16 16 sw a v boost_a gain reg a offset reg a r1 r2 r3 r set_a charta i out_b , i out_c , i out_d r set_b , r set_c , r set_d chartb, chartc, chartd i out_a dac channel b dac channel a dac channel c dac channel d sw b , sw c , sw d v boost_b ,v boost_c ,v boost_d 7.4v to 29.5v reg v sen1 v sen2 + 09225-001 figure 2.
data sheet AD5757 rev. d | page 5 of 44 specifications av dd = v boost _x = 15 v ; dv d d = 2.7 v to 5.5 v; av cc = 4.5 v to 5.5 v ; dc - to - dc converter disabled ; agnd = dgnd = gndsw x = 0 v ; refin = 5 v ; r l = 300 ? ; all specifications t min to t max , unless otherwise noted. table 1 . parameter 1 min typ max unit test conditions/comments current output output current ranges 0 24 ma 0 20 ma 4 20 ma resolution 16 bits accuracy (external r set ) assumes ideal resistor ; see the external current setting resistor section for more information total unadjusted error ( tue) ?0.05 0.009 +0.05 % fsr tue long - term stability 100 ppm fsr drift after 1000 hours, t j = 150c relative accuracy (inl) ?0.006 +0.006 % fsr differential nonlinearity (dnl) ?1 +1 lsb guaranteed monotonic offset error ?0.05 0.005 +0.05 % fsr of fset error drift 2 4 ppm fsr/c gain error ?0.05 0.004 +0.05 % fsr gain tc 2 3 ppm fsr/c full - scale error ?0.05 0.008 +0.05 % fsr full - scale tc 2 5 ppm fsr/c dc crosstalk 0.0005 % fsr external r set accuracy (internal r set ) total unadjusted error (tue) 3 , 4 ?0.14 +0.14 % fsr ?0.11 0.009 +0.11 % fsr t a = 25c tue long - term stability 180 ppm fsr drift after 1000 hours, t j = 150c rel ative accuracy (inl) ?0.006 +0.006 % fsr ?0.004 +0.004 % fsr t a = 25c differential nonlinearity (dnl) ?1 +1 lsb guaranteed monotonic offset error 3 , 4 ?0.0 5 +0.05 % fsr ?0.04 0.007 +0.04 % fsr t a = 25c offset error drift 2 6 ppm fsr/c gain error ?0.12 +0.12 % fsr ?0.06 0.002 +0.06 % fsr t a = 25c gain tc 2 9 ppm fsr/c full - scale error 3 , 4 ?0.14 +0.14 % fsr ?0.1 0.007 +0.1 % fsr t a = 25c full - scale tc 2 14 ppm fsr/c dc crosstalk 4 ?0.011 % fsr internal r set output characteristics 2 current loop compliance voltage v boost_ x ? 2.4 v boost_ x ? 2.7 v outp ut current drift vs. time drift after 1000 hours, ? scale output, t j = 150c 90 ppm fsr external r set 140 ppm fsr internal r set resistive load 1000 ? the dc - to - dc converter has been characterized with a maximum load of 1 k ? , chosen such tha t compliance is not exceeded; see figure 31 and dc - dc maxv bits in table 24 output impedance 100 m? dc psrr 0.02 1 a/v reference input/output reference i nput 2 reference input voltage 4.95 5 5.05 v for specified performance dc input impedance 45 150 m?
AD5757 data sheet rev. d | page 6 of 44 parameter 1 min typ max unit test conditions/comments reference output output voltage 4.995 5 5.005 v t a = 25c reference tc 2 ?10 5 +10 ppm/c output noise (0.1 hz to 10 hz) 2 7 v p - p noise spectral density 2 100 nv/hz at 10 khz output voltage drift vs . time 2 180 ppm drift after 1000 hours, t j = 150c capacitive load 2 1000 nf load current 9 ma see figure 42 shor t - circuit current 10 ma line regulation 2 3 ppm/v see figure 43 load regulation 2 95 ppm/ma see figure 42 thermal hysteresis 2 160 ppm first temperature cycle 5 ppm second temperature cycle dc - to - dc switch switch on resistance 0.425 ? switch leakage current 1 0 na peak current limit 0.8 a oscillator oscillator frequency 11.5 13 14.5 mhz this oscillator is divided down to give the dc - to - dc converter switching frequency maximum duty cycle 89.6 % at 410 khz dc - to - dc switching frequency digital inp uts 2 jedec compliant v ih , input high voltage 2 v v il , input low voltage 0.8 v input current ?1 +1 a per pin pin capacitance 2.6 pf per pin digital outputs 2 sdo, alert v ol , output low voltage 0.4 v sinking 200 a v oh , output high voltage dvdd ? 0.5 v sourcing 200 a high impe dance leakage current ?1 +1 a high impedance output capacitance 2.5 pf fault v ol , output low voltage 0.4 v 10 k? pull - up resistor to dv dd v ol , output low voltage 0.6 v at 2.5 ma v oh , output high voltage 3.6 v 10 k ? p ull - up resistor to dv dd power requirements av dd 9 33 v dv dd 2.7 5.5 v av cc 4.5 5.5 v ai dd 7 7.5 ma di cc 9.2 11 ma v ih = dv dd , v il = d gnd, internal oscillator running, over supplies ai cc 1 ma o ver supplies i boost 5 1 ma per chann el, current output mode , 0 ma output power dissipation 155 mw av dd = 15 v, dv cc = 5 v, dc - to - dc converter enable, current output mode, outputs disabled 1 temperature range: ?40c to +105c; typical at +25c. 2 guaranteed by design and characterization; not production tested. 3 for current outputs with internal r set , the offset, full - scale, and tue measurements exclude dc crosstalk. the measurements are made with all four cha nnels enabled loaded with the same code. 4 see the current output mode with internal r set section for more explanation of the dc crosstalk. 5 efficiency plots in figure 33, figure 34, figure 35 , and figure 36 include the i boost quiescent current.
data sheet AD5757 rev. d | page 7 of 44 ac performance chara cteristics av dd = v boost _x = 15 v ; dv dd = 2.7 v to 5.5 v ; av cc = 4.5 v to 5. 5 v ; dc - to - dc converter disabled ; agnd = dgnd = gndsw x = 0 v ; refin = 5 v ; r l = 300 ? ; all specifications t min to t max , unless otherwise noted. table 2 . parameter 1 min typ max unit test conditions/comments dynamic performance current output output current settling time 15 s to 0.1% fsr (0 ma to 24 ma) see test conditions/ c omment s ms see figure 26, figure 27, and figure 28 output no ise (0.1 hz to 10 hz bandwidth) 0.15 lsb p -p 16- bit lsb, 0 ma to 24 ma range output noise spectral density 0.5 na /hz measured at 10 khz, midscale output, 0 ma to 24 ma range 1 guaranteed by design and characterization; not production tested. timing characteristi cs av dd = v boost _x = 15 v ; dv dd = 2.7 v to 5.5 v ; av cc = 4.5 v to 5.5 v ; dc - to - dc converter disabled ; agnd = dgnd = gndsw x = 0 v ; refin = 5 v; r l = 300 ? ; all specification s t min to t max , unless otherwise noted. table 3 . parameter 1 , 2 , 3 limit at t min , t max unit description t 1 33 ns min sclk cycle time t 2 13 ns min sclk high time t 3 13 ns min sclk low time t 4 13 ns min sync falling edge to sclk falling edge setup time t 5 13 ns min 24 th / 32 nd sclk falling edge to sync rising edge (see figure 54) t 6 198 ns min sync high time t 7 5 ns min data setup time t 8 5 ns min data hold time t 9 20 s min sync rising edge to ldac falling edge (all dacs updated or any channel has digital slew rate control enabled) 5 s min sync rising edge to ldac falling edge (single dac updated) t 10 10 ns min ldac pulse width low t 11 500 ns max ldac falling edge to dac output response time t 12 see the ac performance ch aracteristics section s max dac output settling time t 13 10 ns min clear high time t 14 5 s max clear activation time t 15 40 ns max sclk rising edge to sdo valid t 16 2 1 s min sync rising edge to dac output response time ( ldac = 0) (all dacs updated) 5 s min sync rising edge to dac output response time ( ldac = 0) (single dac updated) t 17 500 ns min ldac falling edge to sync rising edge t 18 8 00 ns min reset pulse width t 19 4 20 s min sync high to next sync low ( d igital slew rate control enabled) (all dacs updated) 5 s min sync high to next sync low ( d igital slew rate control disabled) (single dac updated) 1 guaranteed by design and characterization; not production tested . 2 all input signals are specified with t r ise = t f all = 5 ns (10% to 90% of dv dd ) and timed from a voltage level of 1.2 v. 3 see figure 3 , figure 4 , figure 5 , and figure 6 . 4 this specification applies if ldac is held low during the write cycle; otherwise, see t 9 .
AD5757 data sheet rev. d | page 8 of 44 timing diagrams msb sclk sync sdin ldac ldac = 0 clear 12 24 lsb t 1 i out_x i out_x i out_x t 4 t 6 t 3 t 2 t 5 t 8 t 7 t 10 t 9 t 10 t 11 t 12 t 12 t 16 t 19 t 17 t 13 reset t 18 t 14 09225-002 figure 3. serial interface timing diagram sync msb msb lsb lsb input word specifies register to be read nop condition t 6 t 15 sdin msb lsb undefined selected register data clocked out sdo sclk 24 24 1 1 09225-003 figure 4. readback timing diagram
data sheet AD5757 rev. d | page 9 of 44 sdo disabled r/w sdin sclk sync sdo 12 16 lsb msb dut_ ad1 sdo_ enab dut_ ad0 xxxd15d14 d1d0 status status status status 09225-004 figure 5. status readback during write 200a i ol 200a i oh v oh (min) or v ol (max) to output pin c l 50pf 09225-005 figure 6. load circuit for sdo timing diagram
AD5757 data sheet rev. d | page 10 of 44 absolute maximum rat ings t a = 25c, unless otherwise noted. transient currents of up to 100 ma do not cause scr l atch - up. table 4 . parameter rating av dd , v boost _x to agnd, dgnd ? 0.3 v to +33 v av cc to agnd ? 0.3 v to +7 v dv dd to dgnd ? 0.3 v to +7 v digital inputs to dgnd ? 0.3 v to dv dd + 0.3 v or +7 v (whichever is less) digital outputs to dgnd ? 0.3 v to dv dd + 0.3 v or +7 v (whichever is less) refin, refout to agnd ? 0.3 v t o av dd + 0.3 v or +7 v (whichever is less) i out _x to agnd a gnd to v boost _x or 33 v if using the dc -to - dc circuitry sw x to agnd ?0.3 v to +33 v agnd, gndsw x to dgnd ? 0.3 v to +0.3 v operating temperature range (t a ) industrial 1 ? 40c to +105c storage temperature range ? 65c to +150c junction temperature (t j max) 125c 64- lead lfcsp ja thermal impedance 2 2 8 c/w power dissipation (t j max C t a )/ ja lead temperature jedec i ndustry s tandard soldering j - std - 020 1 power dissipated on chip must be derated to keep the junction temperature below 125c . 2 based on a jedec 4 - layer test board . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the dev ice at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
data sheet AD5757 rev. d | page 11 of 44 pin configuration and fu nction descriptions 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 dgnd reset av dd nc charta igatea comp dcdc_a v boost_a nc i out_a agnd nc chartb nc igateb comp dcdc_b 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 r set_c r set_d refout refin nc chartd igated comp dcdc_d v boost_d nc i out_d agnd nc chartc nc igatec 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 r set_b r set_a refgnd refgnd ad0 ad1 sync sclk sdin sdo dv dd dgnd ldac clear alert fault comp dcdc_c i out_c v boost_c av cc sw c gndsw c gndsw d sw d agnd sw a gndsw a gndsw b sw b agnd v boost_b i out_b 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AD5757 top view (not to scale) pin 1 indicator notes 1. nc = no connect. do not connect to this pin. 2. the exposed pad should be connected to agnd, or alte rnatively, it can be left electrically unconnected. it is recommended that the pad be thermally connected to a copper plane for enhanced thermal performance. 09225-006 figure 7. pin configuration table 5. pin function descriptions pin no. mnemonic description 1 r set_b an external, precision, low drift 15 k current setting resistor can be connected to this pin to improve the i out_b temperature drift performance. see the device features section. 2 r set_a an external, precision, low drift 15 k current setting resistor can be connected to this pin to improve the i out_a temperature drift performance. see the device features section. 3, 4 refgnd ground reference point for internal reference. 5 ad0 address decode for the device under test (dut) on the board. 6 ad1 address decode for the dut on the board. it is not recommended to tie both ad1 and ad0 low when using pec, see the packet error checking section. 7 sync active low input. this is the frame synchronization signal for the serial interface. while sync is low, data is transferred in on the falling edge of sclk. 8 sclk serial clock input. data is clocked in to the input shift register on the falling edge of sclk. this pin operates at clock speeds of up to 30 mhz. 9 sdin serial data input. data must be valid on the falling edge of sclk. 10 sdo serial data output. used to clock data from the serial register in read back mode. see figure 4 and figure 5. 11 dv dd digital supply. the voltage range is from 2.7 v to 5.5 v. 12, 17 dgnd digital ground. 13 ldac load dac, active low input. this is used to update the dac register and consequently the dac outputs. when tied permanently low, the addressed dac data re gister is updated on the rising edge of sync . if ldac is held high during the write cycle, the dac input register is updated, but the dac output update only takes place at the falling edge of ldac (see figure 3). using this mode, all analog outputs can be updated simultaneously. the ldac pin must not be left unconnected. 14 clear active high, edge sensitive input. asserting this pin sets the output current and voltage to the preprogrammed clear code bit setting. only channels enabled to be cleare d are cleared. see the device features section for more information. when clear is active, the dac output register cannot be written to.
AD5757 data sheet rev. d | page 12 of 44 pin no. mnemonic description 15 alert active high output. this pin is asserted when there has been no spi activity on the interface pins for a predetermined time. see the device features section for more information. 16 fau lt active low output. this pin is asserted low when an open circuit in current mode is detected , a short circuit in voltage mode is detected , a p ec error is detected , or an over temperature is detect ed (see the device features section). open - drain o utput. 18 reset hardware reset. active low input. 19 av dd positive analog supply. the v oltage range i s from 10.8 v to 33 v. 20 , 25, 28, 30, 50, 52, 55, 60 nc no connec t . do not connect to this pin. 21 charta hart input connection for dac channel a . 22 igatea optional connection for external pass transistor . should be left unconnected when using the dc - to - dc conve rter . see the external pmos mode section for more information. 23 comp dcdc_a dc -to - dc compensation capacitor. connect a 10 nf capacitor from this pin to ground. used to regulate the feedback loop of the channel a dc -to - dc conver ter. alternatively , if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin ( see the dc -to - dc converter compensation capacitors and the ai cc supply r equirements slewing sections in the device features section for more information ) . 24 v boost_a supply for channel a current output stage ( s ee figure 49 ). to use the dc -to - dc feature of the device, conne ct as shown in figure 56. 26 i out_a current output pin for dac channel a. 27 , 40, 53 agnd ground reference point for analog circuitry. this must be connected to 0 v. 29 chartb hart input connection for dac channel b . 31 igateb optional connection for external pass transi stor . should be left unconnected when using the dc - to - dc converter. see the external pmos mode section for more information. 32 comp dcdc_b dc -to - dc compensation capacitor. connect a 1 0 nf capacitor from this pin to ground. used to regulate the feedback loop of the channel b dc -to - dc converter. alternatively , if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin ( see the dc -to - dc converter compensation capacitors and ai cc supply requirements slewing sections in the device features section for more information ) . 33 i out_b current output pin for dac chann el b. 34 v boost_b supply for channel b current output stage (see figure 49 ). to use the dc - to - dc feature of the device, connect as shown in figure 56. 35 agnd ground reference point for analog circuitry . this pin must be connected to 0 v. 36 sw b switching output for channel b dc -to - dc circuitry . to use the dc -to - dc feature of the device, connect as shown in figure 56. 37 gndsw b ground connection for dc - to - dc switching circuit . this pin should always be connected to ground . 38 gndsw a ground connection for dc - to - dc switching circuit . this pin should always be connected to ground . 39 sw a switching output for channel a dc -to - dc circuitry . to use the dc -to - dc feature of the device , connect as shown in figure 56. 41 sw d switching output for channel d dc -to -dc circuitry . to use the dc -to - dc feature of the device, connect as shown in figure 56. 42 gndsw d ground connections for dc - t o - dc switching circuit . this pin should always be connected to ground . 43 gndsw c ground connections for dc - to - dc switching circuit . this pin should always be connected to ground . 44 sw c switching output for channel c dc -to - dc circuitry . to use the dc -to - dc feature of the device, connect as shown in figure 56. 45 av cc supply for dc - to - dc circuitry . 46 v boost_c supply for channel c current output stage (see figure 49 ). to use the dc -to - dc feature of the device, connect as shown in figure 56. 47 i out_c current output pin for dac channel c. 48 comp dcdc_c dc -to - dc compensation capacitor. connect a 10 nf capacitor from this pin to ground. used to regulate the feedback loop of the c hannel c dc -to - dc converter. alternatively , if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin ( see the dc -to - dc converter compensation capacitors and ai cc supply requirements slewing sections in the device features section for more information ) . 49 igatec optional connection for external pass transi stor . should be left unconnected when using the dc - to - dc converter. see the external pmos mode section for more information.
data sheet AD5757 rev. d | page 13 of 44 pin no. mnemonic description 51 chartc hart input connection for dac channel c . 54 i out_d current output pin for dac channel d. 56 v boost_d supply for channel d current output stage (see figure 49 ). to use the dc -to - dc feature of the device, connect as shown in figure 56. 57 comp dcdc_d dc -to - dc compensation capacitor. connect a 10 nf capacitor from this pin to ground. used to regulate the feedback loo p of the channel d dc -to - dc converter. alternatively , if using an external compensation resistor, place a resistor in series with a cap acitor to ground from this pin ( see the dc -to - dc converter compensation capacitors and ai cc supply requirements slewing sections in the device features section for more information ) . 58 igated optional connection for external pass transis tor . should be left unconnected when using the dc - to - dc conv erter. see the external pmos mode section for more information. 59 chartd hart input connection for dac channel d . 61 refin external reference voltage input. 62 refout internal reference voltage output. it is recommended to pl ace a 0.1 f capacitor between refout and refgnd. refout must be connected to refin to use the internal reference. 63 r set_d an ex ternal, precision, low drift 15 k ? current setting resistor can be connected to this pin to improve the i out_d temperature drift performance. see the device features section. 64 r set_c an external, precision, low drift 15 k ? curr ent setting resistor can be connected to this pin to improve the i out_c temperature drift performance. see the device features section. epad exposed pad. this exposed pad should be connected to agnd , or , alternatively, it can be left electrically unconnected. it is recommended that the pad be thermally connected to a copper plane for enhanced thermal performance.
AD5757 data sheet rev. d | page 14 of 44 typical performance characteristics current outputs ?0.0025 ?0.0020 ?0.0010 0.0005 0 0.0015 ?0.0015 ?0.0005 0.0010 0.0020 0.0025 0 10000 20000 30000 40000 50000 60000 in l error (%fsr) code a v dd = 15v t a = 25c 09225-149 4m a t o 20ma, externa l r set 4m a t o 20ma, externa l r set , with dc- t o-dc converter 4m a t o 20ma, interna l r set 4m a t o 20ma, interna l r set , with dc- t o-dc converter 4m a t o 20ma, externa l r set , externa l pmos mode figure 8. integral nonlinearity vs. code 0 10000 20000 30000 40000 50000 60000 dn l error (lsb) code ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 09225-150 a v dd = 15v t a = 25c 4m a t o 20ma, externa l r set 4m a t o 20ma, externa l r set , with dc- t o-dc converter 4m a t o 20ma, interna l r set 4m a t o 20ma, interna l r set , with dc- t o-dc converter 4m a t o 20ma, externa l r set , externa l pmos mode figure 9. differential nonlinearity vs. code 0 10000 20000 30000 40000 50000 60000 t o t a l unadjusted error (%fsr) code ?0.015 ?0.010 ?0.005 0 0.005 0.010 0.015 0.020 0.025 0.030 0.035 09225-151 a v dd = 15v t a = 25c al l channels enabled 4m a t o 20ma, externa l r set 4m a t o 20ma, externa l r set , with dc- t o-dc converter 4m a t o 20ma, interna l r set 4m a t o 20ma, interna l r set , with dc- t o-dc converter 4m a t o 20ma, externa l r set , externa l pmos mode figure 10 . total unadjusted error vs. code ?0.0010 ?0.0008 ?0.0006 ?0.0004 ?0.0002 0 0.0002 0.0004 0.0006 0.0008 0.0010 in l error (%fsr) 4ma to 20ma range max inl 0ma to 20ma range max inl 0ma to 24ma range max inl 4ma to 20ma range max inl 0ma to 24ma range min inl 0ma to 20ma range min inl av dd = 15v ?40 ?20 0 20 40 60 80 100 temper a ture (c) 09225-152 figure 11 . integral nonlinearity vs. temperature, internal r set ?0.0020 ?0.0015 ?0.0010 ?0.0005 0 0.0005 0.0010 0.0015 0.0020 in l error (%fsr) 4ma to 20ma range max inl 0ma to 20ma range max inl 0ma to 24ma range max inl 4ma to 20ma range min inl 0ma to 24ma range min inl 0ma to 20ma range min inl ?40 ?20 0 20 40 60 80 100 temper a ture (c) av dd = 15v 09225-153 figu re 12 . integral nonlinearity vs. temperature, external r set ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 ?40 ?20 0 20 40 60 80 100 dn l error (lsb) temper a ture (c) av dd = 15v all ranges internal and external r set dnl error max dnl error min 09225-154 figure 13 . differential nonlinearity vs. temperature
data sheet AD5757 rev. d | page 15 of 44 ?0.08 ?0.07 ?0.06 ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0.03 t ot al unadjsuted error (%fsr) ?40 ?20 0 20 40 60 80 100 temper a ture (c) 4ma to 20ma internal r set 4ma to 20ma external r set 0ma to 20ma internal r set 0ma to 20ma external r set 0ma to 24ma external r set 0ma to 24ma internal r set 09225-155 av dd = 15v figure 14 . total unadjusted error vs. temperature ?0.08 ?0.07 ?0.06 ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0.03 full-scale error (%fsr) ?40 ?20 0 20 40 60 80 100 temper a ture (c) av dd = 15v 4ma to 20ma internal r set 4ma to 20ma external r set 0ma to 20ma internal r set 0ma to 20ma external r set 0ma to 24ma external r set 0ma to 24ma internal r set 09225-157 figure 15 . full - scale error vs. temperature ?0.020 ?0.015 ?0.010 ?0.005 0 0.005 0.010 0.015 0.020 offset error (%fsr) ?40 ?20 0 20 40 60 80 100 temper a ture (c) 4ma to 20ma internal r set 4ma to 20ma external r set 0ma to 20ma internal r set 0ma to 20ma external r set 0ma to 24ma external r set 0ma to 24ma internal r set av dd = 15v 09225-158 figure 16 . offset error vs. temperature ?0.06 ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 gain error (%fsr) ?40 ?20 0 20 40 60 80 100 temper a ture (c) 4ma to 20ma internal r set 4ma to 20ma external r set 0ma to 20ma internal r set 0ma to 20ma external r set 0ma to 24ma external r set 0ma to 24ma internal r set av dd = 15v 09225-159 figure 17 . gain error vs. temperature ?0.0020 ?0.0015 ?0.0010 ?0.0005 0 0.0005 0.0010 0.0015 0.0020 0.0025 10 15 20 25 30 in l error (%fsr) supp l y (v) 4ma to 20ma range max inl 4ma to 20ma range min inl t a = 25c 09225-056 figure 18 . integral nonlinea rity error vs. av dd , over supply , external r set ?0.0020 ?0.0025 ?0.0015 ?0.0010 ?0.0005 0 0.0005 0.0010 0.0015 10 15 20 25 30 in l error (%fsr) supp l y (v) 4ma to 20ma range max inl 4ma to 20ma range min inl t a = 25c 09225-057 figure 19 . integral nonlinearity error vs. av dd , over supply , internal r set
AD5757 data sheet rev. d | page 16 of 44 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 10 15 20 25 30 dnl error (lsb) supply (v) dnl error max dnl error min all ranges internal and external r set t a = 25c 09225-162 figure 20 . differential nonlinearity error vs. av dd 0 0.002 0.004 0.006 0.008 0.010 0.012 10 15 20 25 30 t ot al unadjusted error (%fsr) supp l y (v) 4ma to 20ma range max tue 4ma to 20ma range min tue t a = 25c 09225-060 figure 21 . total unadjusted error vs. av dd , external r set 10 15 20 25 30 t ot al unadjusted error (%fsr) supp l y (v) 4ma to 20ma range max tue 4ma to 20ma range min tue t a = 25c ?0.020 ?0.018 ?0.016 ?0.014 ?0.012 ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0 09225-061 figure 22 . total unadjusted error vs. av dd , internal r set ?0.012 ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 10 15 20 25 30 total unadjusted error (%fsr) v boost_x supply (v) 09225-188 t a = 25c external pmos (ntljs4149) 4ma to 20ma range r load = 300? max of tue min of tue figure 23 . total unadjusted error vs. v boost_x , using external pmos mode 6 5 4 3 2 1 0 0 20 15 10 5 current (a) time (s) av dd = 15v t a = 25c r load = 300? 09225-062 figure 24 . output current vs. time on power - up 4 ?10 ?8 ?6 ?4 ?2 0 2 0 1 2 3 4 5 6 voltage (a) time (s) av dd = 15v t a = 25c r load = 300? int_enable 09225-063 figure 25 . output current vs. time on output enable
data sheet AD5757 rev. d | page 17 of 44 0 5 10 15 20 25 30 output current (ma) ?0.50 ?0.25 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 time (ms) 0ma to 24ma range 1k? load f sw = 410khz inductor = 10h (xal4040-103) av cc = 5v t a = 25c i out v boost 09225-167 figure 26 . output current and v boost _x settling time with dc - to- dc conv erter (see figure 56 ) 0 5 10 15 20 25 30 output current (ma) ?0.25 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 time (ms) i out , t a = ?40c i out , t a = +25c i out , t a = +105c 0ma to 24ma range 1k? load f sw = 410khz inductor = 10h (xal4040-103) av cc = 5v 09225-168 figure 27 . output current settling with dc - to - dc converter vs . time and temperature (see figure 56 ) 0 5 10 15 20 25 30 output current (ma) ?0.25 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 time (ms) i out , av cc = 4.5v i out , av cc = 5.0v i out , av cc = 5.5v 0ma to 24ma range 1k? load f sw = 410khz inductor = 10h (xal4040-103) t a = 25c 09225-169 figure 28 . output curr ent settling with dc - to - dc converter vs . time and av cc (see figure 56 ) 0 5 10 15 20 25 ?5 5 0 10 15 20 total unadjusted error (%fsr) time (s) 09225-189 i out (4ma to 20ma step) i out (20ma to 4ma step) t a = 25c external pmos (ntljs4149) 4ma to 20ma range r load = 300? v boost_x = 24v figure 29 . output current settling time with external pmos transistor
AD5757 data sheet rev. d | page 18 of 44 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 0 2 4 6 8 10 12 14 current (ac coupled) (a) time (s) av cc = 5v f sw = 410khz inductor = 10h (xal4040-103) 0ma to 24ma range 1k? load external r set t a = 25c 20ma output 10ma output 09225-170 figure 30 . output current vs . t ime with dc - to - dc converter (see figure 56 ) 8 7 6 5 4 3 2 1 0 0 5 10 15 20 headroom voltage (v) current (ma) 0ma to 24ma range 1k? load f sw = 410khz inductor = 10h (xal4040-103) t a = 25c 09225-067 figure 31 . dc - to- dc converter headroom vs . output current (see figure 56 ) 0 ?120 ?100 ?80 ?60 ?40 ?20 10 100 1k 10k 100k 1m 10m i out_x psrr (db) frequency (hz) av dd = 15v v boost = 15v t a = 25c 09225-068 figure 32 . i out _x psrr vs . frequency
data sheet AD5757 rev. d | page 19 of 44 dc - to - dc block 90 85 80 75 70 65 60 55 50 0 24 20 16 12 8 4 v boost_x efficiency (%) current (ma) 0ma to 24ma range 1k? load external r set f sw = 410khz inductor = 10h (xal4040-103) t a = 25c a v cc = 4.5v a v cc = 5v a v cc = 5.5v 09225-016 figure 33 . efficiency at v boost_x vs. output current (see figure 56 ) 90 85 80 75 70 65 60 55 50 ?40 100 40 60 80 20 0 ?20 v boost_x efficiency (%) temperature (c) 0ma to 24ma range 1k? load external r set av cc = 5v f sw = 410khz inductor = 10h (xal4040-103) 20ma 09225-017 figure 34 . efficiency at v boost_x vs. temperature (see figure 56 ) 80 70 60 50 40 30 20 0 24 20 16 12 8 4 i out_x efficiency (%) current (ma) 0ma to 24ma range 1k? load external r set f sw = 410khz inductor = 10h (xal4040-103) t a = 25c a v cc = 4.5v a v cc = 5v a v cc = 5.5v 09225-018 figure 35 . output efficiency vs. output current (see figure 56 ) 80 70 60 50 40 30 20 ?40 100 40 60 80 20 0 ?20 i out_x efficiency (%) temperature (c) 0ma to 24ma range 1k? load external r set av cc = 5v f sw = 410 khz inductor = 10h (xal4040-103) 20m a 09225-019 figure 36 . output efficiency vs. temperature (see figure 56 ) 0 0.1 0.2 0.3 0.4 0.5 0.6 ?40 ?20 0 20 40 60 80 100 switch resis t ance (?) temper a ture (c) 09225-123 figure 37 . switch resistance vs. temperature
AD5757 data sheet rev. d | page 20 of 44 reference 16 14 12 10 8 6 4 2 0 ?2 0 0.2 0.4 0.6 0.8 1.0 1.2 voltage (v) time (ms) a v dd ref out t a = 25c 09225-010 figure 38 . refout turn - on transient 4 3 2 1 0 ?1 ?2 ?3 0 2 4 6 8 10 refout (v) time (s) av dd = 15v t a = 25c 09225-011 figure 39 . refout output noise (0.1 hz to 10 hz bandwidth) 150 100 50 0 ?50 ?100 ?150 0 5 10 15 20 refout (v) time (ms) av dd = 15v t a = 25c 09225-012 figure 40 . refout output noise (100 khz bandwidth) 5.0000 5.0005 5.0010 5.0015 5.0020 5.0025 5.0030 5.0035 5.0040 5.0045 5.0050 ?40 ?20 0 20 40 60 80 100 refout (v) temperature (c) 30 devices shown av dd = 15v 09225-163 figure 41 . refout vs. temperature ( when the AD5757 is soldered onto a pcb, the reference shifts due to thermal shock on the package. the average output volta ge shift is C 4 mv. measurement of these parts after seven days shows that the outputs typically shift back 2 mv toward their initial value s. this second shift is due to the relaxation of stress incurred during soldering.) 5.002 5.001 5.000 4.999 4.998 4.997 4.996 4.995 0 2 4 6 8 10 refout (v) load current (ma) a v dd = 15v t a = 25c 09225-014 figure 42 . refout vs. load current 5.00000 4.99995 4.99990 4.99980 4.99985 4.99975 4.99970 4.99965 4.99960 10 15 20 25 30 refout (v) av dd (v) t a = 25c 09225-015 figure 43 . refout vs. supply
data sheet AD5757 rev. d | page 21 of 44 general 450 400 350 300 250 200 150 100 50 0 0 1 2 3 4 5 di cc (a) sdin voltage (v) dv cc = 5v t a = 25c 09225-007 figure 44 . di cc vs. logic input voltage 8 7 0 1 2 3 4 5 6 current (ma) voltage (v) ai dd t a = 25c i out = 0ma 10 15 20 25 30 09225-009 figure 45 . ai dd vs. av dd 13.4 13.3 13.2 13.1 13.0 12.9 12.8 12.7 12.6 ?40 ?20 0 20 40 60 80 100 frequency (mhz) temperature (c) dv cc = 5.5v 09225-020 figure 46 . internal oscillator frequency vs. temperature 14.4 14.2 14.0 13.8 13.6 13.4 13.2 13.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 frequency (mhz) voltage (v) dv cc = 5.5v t a = 25c 09225-021 figure 47 . internal oscillator frequency vs. dv cc supply voltage
AD5757 data sheet rev. d | page 22 of 44 terminology relative accuracy or integral nonlinearity (inl) for the dac, relative accuracy, or integral nonlinear ity , is a measure of the maximum deviation, in lsbs, from the best fit line th r ough the dac transfer function. a typical inl vs. code plot is shown in figure 8 . differential nonlinearity (dnl) differential nonlinearity (d nl) is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic by design. a typical dnl vs. code pl ot is shown in figure 9 . monotonicity a dac is monotonic if the output either increases or remains constant for increasing digital input code. the AD5757 is monotonic over its full operating temperature range. offset error o ffset error is the deviation of the analog output from the ideal zero - scale output when all dac registers are loaded with 0x0000. gain error this is a measure of the span error of the dac. it is the devia - tion in slope of the dac transfer characteristic from the ideal, expressed in % fsr. gain tc this is a measure of the change in gain error with changes in temperature. gain tc is expressed in ppm fsr/c. full - scale error full - scale error is a measure of the output error when full - scale code is loaded to the dac register. ideally, the output should be full - scale ? 1 lsb. full - scale error is expressed in percent of full - scale range (% fsr). full - scale tc full - scale tc is a measure of the change in full - scale error with changes in temperature and is expressed in ppm fsr/c. total unadjusted error total unadjusted error (tue) is a measure of the output error taking all the various errors into account, including inl error, offset error, gain error , temperature, and time. tue is expressed in % fsr. dc crosstalk this is the dc change in the output level of one dac in response to a change in the output of another dac. it is measured with a full - scale output change on one dac while monitoring another dac, which is at midscale. current loop compliance voltage the maximum vo ltage at the i out _x pin for which the output current is equal to the programmed value. voltage reference thermal hysteresis voltage reference thermal hysteresis is the difference in output voltage measured at +25c compared to the output voltage measured a t +25c after cycling the temperature from +25c to ?40c to +105c and back to +25c. the hysteresis is specified for the first and second temperature cycles and is expressed in ppm . power - on glitch energy power - on glitch energy is the impulse injected in to the analog output when the AD5757 is powered - on. it is specified as the area of the glitch in nv - sec. see figure 24. power supply rejection ratio (psrr) psrr indicates how the output of the dac is affected by changes in the pow er supply voltage. reference tc reference tc is a measure of the change in the reference output voltage with a change in temperature. it is expressed in ppm/c. line regulation line regulation is the change in reference output voltage due to a specified ch ange in supply voltage. it is expressed in ppm/v. load regulation load regulation is the change in reference output voltage due to a specified change in load current. it is expressed in ppm/ma. dc -to - dc converter headroom this is the difference between the voltage required at the current output and the voltage supplied by the dc - to - dc converter. see figure 31. output efficiency cc cc load ai av r i out 2 this is defined as the power delivered to a channels load vs . the power delivere d to the channel s dc - to - dc input. efficiency at v boost_x cc cc x boost out ai av v i _ this is defined as the power delivered to a channels v boost _x supply vs . the power delivered to the channel s dc - to - dc input. the v boost _x quiescent current is considered pa rt of the dc - to - dc converters losses.
data sheet AD5757 rev. d | page 23 of 44 theory of operation the AD5757 is a quad, p recision digital - to - current loop converter designed to meet the requirements of industrial process control applications. it provides a high precision, fully integrated, lo w cost , single - chip solution for generating current loop outputs. t he current ranges available are 0 ma to 20 ma, 0 ma to 24 ma , and 4 ma to 20 ma . the desired output configuration is user selectable via the dac c ontrol r egister. on - chip dynamic power cont rol minimizes package power dissipation in current mode. dac architecture the dac core architecture of the AD5757 consists of two matched dac sections. a simplified circuit diagram is shown in figure 48 . the four msbs of the 16 - bi t data - word are decoded to drive 15 switches, e1 to e15. each of these switches connects one of 15 matched resistors to either ground or the reference b uffer output. the remaining 12 bits of the data - word drive switch s0 to switch s11 of a 12 - bit voltage m ode r - 2r ladder network. 12-bit r-2-r ladder four msbs decoded in t o 15 equa l segments 2r 2r s0 s1 s 1 1 e1 e2 e15 v out 2r 2r 2r 2r 2r 09225-069 figure 48 . dac ladder structure the voltage output from the dac core is converted to a current (see figure 49) , which is then mirrored to the supply rail so that the application simply sees a current source output . the current output s are supplied by v boost _x . 16-bit dac v boost_x r2 t2 t1 r3 i out_x r set a1 a2 09225-071 figure 49 . voltage - to- current conversion circuitry reference buffers the AD5757 can operate with either an external or internal reference. the re ference input requires a 5 v reference for specified performance . this input voltage is then buffered before it is applied to the dac. power - on state of the AD5757 on power - up of the AD5757 , the i out _x pins are in tri state mode. after device power - on or a device reset, it is recommended to wait 100 s or more before writing to the device to allow time for internal calibrations to take place. serial interface the AD5757 is controlled over a versatile 3 - wire serial interface that operates at clock rates of up to 30 mhz and is compatible with spi , qspi, microwire, and dsp standards. data coding is always straight binary. input shift register the input shift register is 24 bits wide. data is loaded into the device msb first as a 24 - bit word under the control of a serial clock input, sclk. data is clocked in on the falling edge of sclk. if packet error checking, or pec (see the device features section) , is enabled , an additional eight bits must be written to the AD5757 , creating a 32 - b it serial interface. there are two ways in which the dac ou tputs can be updated: individual updating or simultaneous updating of all dacs . individual dac updating in this mode, ldac is held low while data is being clocked into the da c d ata r egister. the addressed dac output is updated on the rising edge of sync . see table 3 and figure 3 for timing information. simultaneous updating of all dacs in this mode, ldac is held high while data is being clocked into the dac d ata r egister. only the first write to each channel s dac data register is valid after ldac is brought high. any subse - quent writes while ldac is still held high are ignored, al though they are loaded into the dac data register. all the dac outputs are updated by taking ldac low after sync is taken high. v out_x dac register interface logic output i/v amplifier ldac sdo sdin 16-bit dac v refin sync dac data register offset and gain calibration dac input register sclk 09225-072 figure 50 . simplified serial interface of input loading circuitry for one dac channel
AD5757 data sheet rev. d | page 24 of 44 transfer function for the 0 ma to 20 ma, 0 ma to 24 ma, and 4 ma to 20 ma current output ranges, the output current is respectively expressed as d i n out ? ? ? ? ? ? = 2 ma 20 d i n out ? ? ? ? ? ? = 2 ma 24 ma 4 2 ma 16 + ? ? ? ? ? ? = d i n out where: d is the decimal equivalent of the code loaded to the dac. n is the bit resolution of the dac.
data sheet AD5757 rev. d | page 25 of 44 registers table 6 shows an overview of the r egisters for the AD5757 . table 6 . data , control , and readback registers for the AD5757 register description data dac data register ( 4) used to write a dac code to each dac channel. AD5757 d ata bits = d15 to d0 . there are four dac d ata r egisters, one per dac c hannel. gain register ( 4) used to program gain trim , on a per channel basis. AD5757 data bits = d15 to d0. there are four g ain r egisters, one per dac channel. offset register ( 4) used to program offset trim, on a per channel basis. AD5757 data bits = d15 to d 0. there are four o ffset r egisters, one per dac channel. clear code register ( 4) used to program c lear c ode on a per channel basis. AD5757 data bits = d15 to d0. there are four c lear c ode r egisters, one per dac channel. control main control register used to c onfigure the part for main operation. sets functions such as status readback during write, enable s output on all channels simultaneously, power s on all dc -to - dc converter blocks simultaneously, and enables and sets conditions of the watchdog timer . see the device features s ection for more details. software register has three func tions. used to perform a reset, to toggle the user bit and , as part of the watchdog timer feature , to verify correct data communication operatio n. slew rate control register ( 4) use d to program the slew rate of the output. there are four s lew r ate c ontrol r egisters, one per channel. dac control register ( 4) these registers are used to control the following : set the output range, for example, 4 ma to 20 ma . set whether an i nternal/ e xternal sense r esistor is used . en able/disable a channel for clear. enable/disable internal circuitry on a per channel basis. enable/ d isable output on a per chann el basis. power on dc -to - dc converter s on a per chann el basis. there are four dac c ontrol r egisters, one per dac channel. dc -to - dc control register use to set the dc - to - dc c ontrol parameters. can control dc -to - dc max imum voltage, phase , and frequency. readback status register this contains any fault inf ormation, as well as a user toggle bit.
AD5757 data sheet rev. d | page 26 of 44 programming sequence to write/enable the output correctly to correctly write to a nd set up the part from a power - on condition , use the following sequence : 1. perform a hardware or sof tware reset after initial powe r - on. 2. the dc - to - dc converter supply block must be configured. set the dc - to - dc switching frequency, max imum output voltage allowed , and the phase that the four dc - to - dc channels clock at. 3. configure the dac c ontrol r egister on a per channel basis. the out put range is selected, and the dc - to - dc converter block is enabled (dc_dc bit) . other control bits can be configured at this point . set the int_enable bit ; however, the output enable bit (outen) should not be set. 4. write the required code to the dac data r egister. this implement s a full dac calibration internally. allow at least 200 s before step 5 for reduced output glitch. 5. write to the dac c ontrol r egister again to enable the out put (set the outen bit). a flow chart of this sequence is shown in figure 51. power on. step 1: perform a software/hardware reset. step 4: write to each/all dac data registers. allow at least 200s between step 3 and step 5 for reduced output glitch. step 2: write to dc-to-dc control register to set dc-to-dc clock frequency, phase, and maximum voltage. step 3: write to dac control register. select the dac channel and output range. set the dc_dc bit and other control bits as required. set the int_enable bit but do not select the outen bit. step 5: write to dac control register. reload sequence as in step 3 above. this time select the outen bit to enable the output. 09225-073 figure 51 . programming sequence for enabling the output correctly changing and reprogr amming the range when changing between ranges , the same sequence as described in the prog ramming sequence to write/enable the output correctly section should be used. it is recommended to set the rang e to zero scale prior to disabling the output. because the dc - to - dc switching frequency, max imum voltage , and phase have already been selected, t here is no need to reprogram the s e. a flow chart of this sequence is shown in figure 52. channe l ?s output is enabled. ste p 3: write v alue t o the dac d at a register. ste p 1: write t o channe l ?s dac d at a register. set the output t o 0v (zero or midscale). ste p 2: write t o dac contro l register. disable the output (outen = 0), and set the new output range. kee p the dc_dc bit and the int_enable bit se t . ste p 4: write t o dac contro l register. reload sequence as in ste p 2 above. this time select the outen bit t o enable the outpu t . 09225-074 figure 52 . steps for changing the output range
data sheet AD5757 rev. d | page 27 of 44 data registers the input register is 24 bits wide. when pec is enabled , the input register is 32 bits wide, with the last eight bits correspond - ing to the pec code ( see the packet error checking section for more information on pec ) . when writing to a data register , the format in table 7 must be used. dac data register when writing to the AD5757 dac data registers, d15 to d0 are used for the dac data bits. table 9 shows the register format and table 8 describes the function of bit d23 to bit d16. table 7 . writing to a data register msb lsb d23 d22 d21 d20 d19 d18 d17 d16 d15 to d0 r/ w dut_ad1 dut_ad0 dreg2 dreg1 dreg0 dac_ad1 dac_ad0 data table 8 . input register decode bit description r/ w indicates a read from or a write to the addressed register. dut_ad1, dut_ad0 used in association with the e xternal p ins , ad1 and ad0 , to determine which AD5757 device is being addressed by the system controller. it is not recommended to tie both ad1 and ad0 low when using pec, see the packet error checking section. dut_ad1 dut_ad0 function 0 0 addresses part with pin ad1 = 0, pin ad0 = 0 0 1 addre sses part with pin ad1 = 0, pin ad0 = 1 1 0 addresses part with pin ad1 = 1, pin ad0 = 0 1 1 addresses part with pin ad1 = 1, pin ad0 = 1 dreg2, dreg1, dreg0 selects whether a data register or a control register is written to. if a control register is selected, a further decode of creg bits (see table 16) is required to select the particular control register, as follows . dreg2 dreg1 dreg0 function 0 0 0 write to dac data register (individual channel write) 0 1 0 write to gain register 0 1 1 write to gain register (all dacs) 1 0 0 write to offset register 1 0 1 write to offset register (all dacs) 1 1 0 write to clear code register 1 1 1 write to a control register dac_ad1, dac_ad0 these bits are used to decode t he dac channel . dac_ad1 dac_ad0 dac channel/ register address 0 0 dac a 0 1 dac b 1 0 dac c 1 1 dac d x x these are dont cares if they are not relevant to the operation being performed. table 9 . programming the dac data registers msb lsb d23 d22 d21 d20 d19 d18 d17 d16 d15 to d0 r/ w dut_ad1 dut_ad0 dreg2 dreg1 dreg0 dac_ad1 dac_ad0 dac data
AD5757 data sheet rev. d | page 28 of 44 gain register the 16- bi t g ain r egister , as shown in table 10, allows t he user to adjust the gain of each channel in steps of 1 lsb . this is done by setting the dreg[2:0] bits to 010. it is possible to write the same gain code to all four dac channels at the same time by setting the dreg [2:0] bits to 011. the g ain r egister co ding is straight binary as shown in table 11. the default code in the g ain r egister is 0x ffff . in theory , the gain can be tuned across the full range of the output. in practice, the maximum recom - mended gain trim is about 50% of p rogrammed range to maintain accuracy. see the digital offset and gain control section for more information. offset register the 16 - bit offset register , as shown in table 12, allows the user to adjust t he offset of each channel by ?32,768 lsbs to +32,767 lsbs in steps of 1 lsb . this is done by setting the dreg[2:0] bits to 100. it is possible to write the same offset code to all four dac channels at the same time by setting the dreg [2:0] bits to 101 . the o ffset r egister coding is straight binary as shown in table 13 . the default code in the o ffset r egister is 0x8000 , which result s in zero offset programmed to the output. see the digital offset and gain co ntrol section for more information. clear code register the 16 - bit clear code register allows the user to set the clear value of each channel as shown in table 14. it is po ssible, via software, to enable or disable on a per chann el basis which channels are cleared when the clear pin is activated. the default clear code is 0x0000. see the asynchronous clear section for more information. table 10 . programming the gain register r/ w dut_ad1 dut_ad0 dreg2 dreg1 dreg0 dac_ad1 dac_ad0 d15 to d0 0 device address 0 1 0 dac channel address gain a djustment table 11 . gain register gain adjustment g15 g14 g13 g12 to g4 g3 g2 g1 g0 +65 , 535 lsbs 1 1 1 1 1 1 1 1 +65 , 534 lsbs 1 1 1 1 1 1 0 0 1 lsb 0 0 0 0 0 0 0 1 0 lsbs 0 0 0 0 0 0 0 0 table 12 . programming the offset register r/ w dut_ad1 dut_ad0 dreg2 dreg1 dreg0 dac_ad1 dac_ad 0 d15 to d0 0 device address 1 0 0 dac channel address offset a djustment table 13 . offset register options offset adjustment of15 of14 of13 of12 to of4 of3 of2 of1 of0 +32 , 76 7 lsbs 1 1 1 1 1 1 1 1 +32 , 766 lsbs 1 1 1 1 1 1 0 0 no adjustment ( default ) 1 0 0 0 0 0 0 0 ?32 , 767 lsbs 0 0 0 0 0 0 0 0 ?32 , 768 lsbs 0 0 0 0 0 0 0 0 table 14 . programming the clear code register r/ w dut_ad1 dut_ad0 dre g2 dreg1 dreg0 dac_ad1 dac_ad0 d15 to d0 0 device address 1 1 0 dac c hannel a ddress c lear c ode
data sheet AD5757 rev. d | page 29 of 44 control registers when writing to a control register , the format shown in table 15 must be us ed. see tab le 8 for information on the configuration of bit d23 to bit d16. the control registers are addressed by setting the dreg [2:0] bits to 111 and then setting the creg [2:0] bits to the appropriate decode address for that register, according to table 16 . these creg bits select among the various control registers. main control register the main control register options are shown in table 17 and table 18 . see the device features section for more information on the features controlled by the main control register. table 15 . writing to a control register msb lsb d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 to d0 r/ w dut_ad1 dut_ad0 1 1 1 dac_ad1 dac_ad0 creg2 creg1 creg0 data table 16 . register access decode creg2 (d15) creg1 (d14) creg0 (d13) function 0 0 0 slew r ate c ontrol r egister (one per channel) 0 0 1 main c ontrol r eg ister 0 1 0 dac c ontrol r egister (one per channel) 0 1 1 dc -to - dc c ontrol r egister 1 0 0 software register table 17 . programming the main control register msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 to d0 0 0 1 0 statread ewd wd1 wd0 x 1 x 1 outen_all dc dc _ all x 1 1 x = dont care. table 18 . main control register functions bit description statread enable status readback during a write. see the device features section. statread = 1, e nable . statread = 0, d isable (default) . ewd enable w atchdog t imer. see the device features section for more information. ewd = 1, e nable w atchdog . ewd = 0, d isable w atchdog (default) . wd1, wd0 timeout s el ect b its. used to select the timeout period for the watchdog timer. wd1 wd0 timeout period (ms) 0 0 5 0 1 10 1 0 100 1 1 200 outen_all enables the output on all four dac s simultaneously. do not use the outen _ all bit when using the outen bit in the dac c ontrol register . dcdc _ all when set, p owers up the dc - to - dc converter on all four channels s imultaneously. to p ower down the dc -to - dc converters , all channel outputs must first be disabled. do not use the dc d c_ all bit when using the dc_dc bit in the dac control register .
AD5757 data sheet rev. d | page 30 of 4 4 dac control register the dac c ontrol r egister is used to configure each dac c hannel. the dac c ontrol r egister options are shown in table 19 and table 20. table 19 . programming dac control register d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 x 1 x 1 x 1 x 1 int_enable clr_en outen rset dc_ dc x 1 r2 r1 r0 1 x = dont care. table 20 . dac control register functions bi t description int_enable powers up the dc - to - dc converter , dac , and internal amplifiers for the selected channel. does not enable the output. can only be done on a per channel basis. it is recommended to set this bit and allow a > 200 s delay before enabl ing the output because this result s in a reduced output enable glitch. plots of this glitch can be found in figure 25. clr_en per channel c lear e nable bit. selects if this channel clear s when the clear pin is activated. clr_en = 1, channel clear s when the part is cleared. clr_en = 0, channel does not clear when the part is cleared (default) . outen enables/ d isables the selected output channel . outen = 1, e nables the channel . outen = 0, d isable s the channel (default) . rset select s an internal or external current sense resistor for the selected dac channel . rset = 0 , s elects the external r esistor (default) . rset = 1 , selects the i nternal r esistor . dc_dc powers the dc - to - dc converter on the selected channel. dc_dc = 1, p ower up the dc -to - dc converter . dc_dc = 0, p ower down the dc -to - dc converter (default) . this allows per channel dc - to - dc converter power - up/ power - d own. to power down the dc -to - dc converter , the outen and int_enable bits must also be set to 0. all dc -to - dc converte rs can also be powered up simultaneously using the dcdc_ all bit in the m ain c ontrol r egister. r2, r1, r0 selects the output range to be enabled. r2 r1 r0 output range selected 1 0 0 4 ma to 20 ma c urrent r ange 1 0 1 0 ma to 20 ma c urrent r ange 1 1 0 0 ma to 24 ma c urrent r ange
data sheet AD5757 rev. d | page 31 of 44 software register the s oftware r egister has three functions. it allows the user to perform a software reset to the part. it can be used to set the user toggle bit, d11 , in the s tatus r egister. it is also used as part of the watchdog feature when it is enabled. this feature is useful to ensure that communication has not been lost between the mcu and the AD5757 and that the datapath l ines are working properly (that is, sdi n , sclk , and sync ). when th e watchdog feature is enabled , the user must write 0x195 to the s oftware r egister within the timeout period. if this command is not received within the timeout period, the alert pin signal s a fault condition. this is only required when the w atchdog t imer f unction is enabled. dc - to - dc control register the dc - to - dc control register allows the user control over the dc - to - dc switching frequency and phase, as well as the maximum allowable dc - to - dc output voltage. the dc - to - dc control register options are shown in table 23 and table 24. table 21 . programming the software register msb lsb d15 d14 d13 d12 d11 to d0 1 0 0 user p rogram reset code /spi code table 22 . software register functions bit description user program this bit is mapped to bit d11 of the s tatus r egister. when this bit is set to 1 , bit d11 of the s tatus r egister is set to 1. likewise , when d12 is set to 0 , bit d11 of the s tatus r egister is a lso set to zero. this feature can be used to ensure that the spi pins are working correctly by writing a known bit value to this register and reading back the corresponding bit from the s tatus r egister. reset code /spi code option description reset code writing 0x555 to d [11: 0 ] performs a reset of the AD5757 . spi code if the w atchdog t imer feature is enabled, 0x195 must be written to the s oftware register (d11 to d0) within the programmed timeout period . table 23 . programming th e dc -to - dc control register msb lsb d15 d14 d13 d12 to d7 d6 d5 to d4 d3 to d2 d1 to d0 0 1 1 x 1 dc - dc comp dc - dc phase dc - dc freq dc - dc maxv 1 x = dont care. table 24 . dc -to - dc control register options bit description dc - dc comp selects between an internal and external compensation resistor for the dc - to - dc converter . see the dc - to - dc converter compensation capacitors and ai cc supply requirements slewing sections in t he device features section for more information. 0 = s elects the internal 150 k ? compensation resistor ( d efault) . 1 = b ypasses the internal compensation resistor for the dc -to - dc converter. in this mode , an external dc -to - dc compe nsation resistor must be used ; this is placed at the comp dcdc _x pin in series with the 10 nf dc -to - dc compensation capacitor to ground. typically , a ~50 k? resistor is recommended . dc - dc phase user p rogrammable dc -to - dc converter p hase ( between c hannels) . 00 = a ll dc -to - dc converters clock on the same edge (default) . 01 = chan nel a and chan nel b clock on the same edge, chan nel c and chan nel d clock on opposite edge s . 10 = chan nel a and chan nel c clock on the same edge, chan nel b and chan nel d clock on oppo site edge s . 11 = chan nel a, chan nel b, chan nel c, and chan nel d clock 90 out of phase from each other . dc - dc freq dc -to - dc s witching f requency ; these are divided down from the internal 13 mhz oscillator ( see figure 46 and figure 47) . 00 = 250 10% kh z . 01 = 410 10% kh z (default) . 10 = 650 10% kh z . dc -dc maxv maximum allowed v boost _x voltage supplied by the dc - to - dc converter . 00 = 23 v + 1 v/ ? 1 .5 v (default) . 01 = 24.5 v 1 v . 10 = 27 v 1 v . 11 = 29.5 v 1v .
AD5757 data sheet rev. d | page 32 of 44 slew rate control register this register is used to program the slew rate control for the selected dac channel. the slew rate control is enabled/ disabled and programmed on a per channel basis. see table 25 and t he digital slew rate control section for more information. readback operation readback mode is invoked by setting the r/ w bit = 1 in the serial input register write. see table 26 fo r the bits associated with a readback operation. the dut_ad1 and dut_ad0 bits, in association with bits rd[4:0], select the register to be read. the remaining data bits in the write sequence are dont care s. during the next spi transfer (see figure 4 ), the data appearing on the sdo output contains the data from the previously addressed register. this second spi transfer should either be a request to read yet another register on a third data tran sfer or a no operation command. the no operation command for dut_ad[1:0] = 00 is 0x1ce000 ; for other dut addresses , bit d22 and bit d21 are set accordingly. readback example to read back the gain register of device 1, channel a on the AD5757 , implement the following sequence: 1. write 0xa80000 to the AD5757 input register. this configures the AD5757 device address 1 for read mode with the gain register of channel a selected. all the data bits, d15 to d0, are dont care s. 2. follow with another read command or a no operation command ( 0x3ce000 ) . du ring this command, the data from the channel a gain register is clocked out on the sdo line. table 25 . programming the slew rate control register d15 d14 d13 d12 d11 to d7 d6 to d3 d2 to d0 0 0 0 sren x 1 sr_clock sr_step 1 x = do nt care. table 26 . input shift register contents for a read operation d23 d22 d21 d20 d19 d18 d17 d16 d15 to d0 r/ w dut_ad1 dut_ad0 rd4 rd3 rd2 rd1 rd0 x 1 1 x = dont care. table 27. read address decoding rd4 rd3 rd2 rd1 rd0 function 0 0 0 0 0 read dac a d ata r egister 0 0 0 0 1 read dac b d ata r egister 0 0 0 1 0 read dac c d ata r egister 0 0 0 1 1 read dac d d ata r egister 0 0 1 0 0 read dac a c ontrol r egister 0 0 1 0 1 read dac b c ontrol r egister 0 0 1 1 0 read dac c c ontrol register 0 0 1 1 1 read dac d c ontrol r egister 0 1 0 0 0 read dac a g ain r egister 0 1 0 0 1 read dac b g ain r egister 0 1 0 1 0 read dac c g ain r egister 0 1 0 1 1 read dac d g ain r egister 0 1 1 0 0 read daca offset register 0 1 1 0 1 read dac b offset register 0 1 1 1 0 read dac c offset register 0 1 1 1 1 read dac d offset register 1 0 0 0 0 clear dac a c ode r egister 1 0 0 0 1 clear dac b c ode r egister 1 0 0 1 0 clear dac c c ode r egis ter 1 0 0 1 1 clear dac d c ode r egister 1 0 1 0 0 dac a slew rate control register 1 0 1 0 1 dac b slew rate control register 1 0 1 1 0 dac c slew rate control register 1 0 1 1 1 dac d slew rate control register 1 1 0 0 0 read s tatus r egister 1 1 0 0 1 read m ain c ontrol r egister 1 1 0 1 0 read dc - to - dc c ontrol r egister
data sheet AD5757 rev. d | page 33 of 44 status register the s tatus r egister is a read only register. this register contains any fault information as a well as a ramp active bit and a u ser t oggle b it. when the statread bit in the m ain c ontrol r egister is set , the s tatus r egister contents can be read back on the sdo pin during every write sequence. alternat iv ely, if the statread bit is not set , the s tatus r egister can be read using the normal readback operation. table 28 . decoding the status register msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dc - dcd dc - dcc dc - dcb dc - dca user toggle pec error ramp active over temp x 1 x 1 x 1 x 1 i out_d f ault i out_c f ault i out_b f ault i out_a f ault 1 x = dont care. table 29 . status register options bit description dc - dcd t his bit is set on channel d if the dc -to - dc convert er cannot maintain compliance (i t may be reaching its v max voltage). in this case , the i out_d f ault bit is also set. see the dc - to - dc converter v max functionality sect ion for more information on this bit s operation under this condition. dc - dcc this bit is set on channel c if the dc -to - dc converter cannot maintain complian ce (it may be reaching its v max voltage). in this case, the i out_ c fault bit is also set. see the dc - to - dc converter v max functionality section for more information on this bits operation under this condition. dc - dcb this bit is set on channel b if the dc -to - dc converter cannot maintain compliance (it may be reaching its v max voltage). in this case, the i out_ b fault bit is also set. see the dc - to - dc converter v max functionality section for more informati on on this bits operation under this condition. dc -dc a this bit is set on channel a if the dc -to - dc converter cannot maintain compliance (it may be reaching its v max voltage). in this case, the i out_ a fault bit is also set. see the dc - to - dc converter v max functionality section for more information on this bits operation under this condition. user t oggle user t oggle bit . this bit is set or cleared via the software register. this can be used to verify data communications if need ed. pec error denotes a pec e rror on the last data - word received over the spi interface. ramp active this bit is set while any one of the output channels is slewing (slew rate control is enabled on at least one channel) . over temp this bit is set if th e AD5757 core temperature exceeds approx imately 150 c. i out_d fault this bit is set if a fault is detected on the i out _d pin. i out_c fault this bit is set if a fault is detected on the i out _c pin. i out_b fault this bit is set if a fault is detected on t he i out _ b pin. i out_a fault this bit is set if a fault is detected on the i out _a pin.
AD5757 data sheet rev. d | page 34 of 44 device features output fault the AD5757 is equipped with a fault pin, an active low open - drain output allowing several AD5757 devices to be connect ed together to one pull - up resistor for global fault detection. the fault pin is forced active by any one o f the following fault scenarios: ? the v oltage at i out _x attempts to rise above the compliance range, due to an open - loop circuit or insufficient power supply voltage. the internal circuitry that develops the fault output avoids using a comparator with window ed limits because this require s an actual output error before the fault output becomes active. instead, the sign al is generated when the internal amplifier in the output stage has less than approximately 1 v of remaining drive capability. thus , the fault output activates slightly before the compliance limit is reached. ? an interface error is detecte d due to a pec failure. see the packet error checking section. ? if the core temperature of the AD5757 exceeds approx imately 150c. the i out _x f ault , pec error , and over temp bits of the s tatus r egister are used in conjunction with the fault output to inform the user which one of the fault conditions caused the fault output to be activated. digital offset and g ain control each dac channel has a gain (m) and offset (c) register, which allow trimmin g out of the gain and offset errors of the entire signal chain. data from the dac d ata r egister is operated on by a digital multiplier and adder controlled by the contents of the m and c registers. the calibrated dac data is then stored in the dac input re gister. dac register dac input register m register c register 09225-075 figure 53 . digital offset and gain control although figure 53 indicates a multiplier and adder for each channel, there is only one multiplier and one adder in the device, and they are shared am ong all four channels. this has implications for the update speed when several channels are updated at once ( see table 3 ) . each time data is written to the m or c register , the output is not automatically updated. instead , the ne xt write to the dac channel use s these m and c values to perform a new calibration and automatically update s the channel. the output data from the calibration is routed to the dac input register. this is then loaded to the dac as described in the theory of operation section. both the gain r egister and the o ffset r egister have 16 bits of resolution. the correct method to calibrate the gain/offset is to first calibrate out the gain and then calibrate the offset. the value (in decim al) that is written to the dac input register can be calculated by 15 16 2 2 ) 1 ( ? + + = c m d code r dacregiste (1) where: d is the code loaded to the dac channel s input register. m is the code in the g ain r egister ( default code = 2 16 C 1 ). c is the code in the o ffset r egister ( default code = 2 15 ) . status readback duri ng a write the AD5757 has the ability to read back the s tatus r egister contents during every write sequence. this feature is enabled via the statread bit in the m ain c ontrol r egister. this allows the user to conti nuously monitor the s tatus r egister and act quickly in the case of a fault. when s tatus r eadback d uring a w rite is enabled , the contents of the 16 - bit s tatus register ( s e e table 29) are output on the sdo pin , as shown in figure 5 . the AD5757 power s up with this feature disabled. when this is enabled , the normal readback feature is not available, except for the status register. to read back any other register , clear the statread bit first before following the readback sequence. statread can be set high again after the register read. asynchronous clear clear is an active high , edge - sensitive input that allows th e output to be cleared to a pre pro grammed 16 - bit code. this code is user programmable via a per c hannel 16 - bit c lear c ode r egister. f or a channel to clear, that channel must be enabled to be cleared via the clr_en bit in the channel s dac c ontrol r egister. if the channel is not enabled to be cleared , the output remain s in its current state independent of the clear pin level. when the clear signal is returned low, the relevant outputs remain cleared until a new value is programmed. packet error checkin g to verify that data has been received correctly in noisy environ - ments, the AD5757 offers the optio n of packet error checking based on an 8 - bit cyclic redundancy check (crc - 8) . the device controlling the AD5757 should generate an 8 - bit frame check sequence using the polynomial c ( x ) = x 8 + x 2 + x 1 + 1 this is added to the end of the data - word, and 32 bit s are sent to the AD5757 before taking sync high. if the AD5757 sees a 32- bit frame, it perform s the error check when sync goes high. if the check is valid, the data is written to the selected register.
data sheet AD5757 rev. d | page 35 of 44 if th e error check fails, the fault pin go es low and the pec error bit in the s tatus r egister is set. after reading the s tatus r egister, fault return s high (assuming there are no other faults) , and the pec error bit is cleare d automatically. it is not recommended to tie both ad1 and ad0 low as a short low on sdin could possibly lead to a zero - scale update for dac a. sdin sync sclk upd a te on sync high msb d23 lsb d0 24-bit d at a 24-bit d at a transfer?no error checking sdin f au l t sync sclk upd a te on sync high on l y if error check p assed f au l t pin goes low if error check f ails msb d31 lsb d8 d7 d0 24-bit d at a 8-bit crc 32-bit d at a transfer with error checking 09225-008 figure 54 . pec timing the pec can be used for both transmit and receive of data packe ts. if s tatus r eadback d uring a w rite is enabled, the pec values returned during the s tatus r eadback d uring a w rite operation should be ignored. if s tatus r eadback d uring a w rite is disabled, th e user can still use the normal readback operation to monitor s tatus r egister activity with pec . watchdog t imer when enabled, an on - chip watchdog timer generate s an alert signal if 0x195 has not been written to the s oftware r egister within the programmed timeout period. this feature is useful to ensure that communic ation has not been lost between the mcu and the AD5757 and that these datapath lines are working properly ( that is, sdi n , sclk , and sync ). if 0x195 is not received by the s oftware r egister within the timeout period, the alert pin si gnal s a fault condition. the alert signal is active high and can be connected directly to the clear pin to enable a clear in the event that communication from the mcu is lost . the watchdog timer is enabled , and the timeout period (5 ms , 10 ms , 1 0 0 ms, or 200 ms) is set in the main control register ( s ee table 17 and table 18). output alert the AD5757 is equipped with a n alert pin . this is a n active high cmos output. the AD5757 also has an internal watchdog timer. when enabled, it monitor s spi communications. if 0x195 is not received by the s oftware r egister within the timeout period, the alert pin go es active. internal reference the AD5757 contains an int egrated 5 v voltage reference with initial accuracy of 5 mv max imum and a temperature drift coefficient of 10 ppm max imum . the reference voltage is buffered and externally available for use elsewhere within the system. refout must be connected to refin to use the internal reference. external c urrent s et ting r esistor referring to figure 49, r set is an internal sense resistor as part of the voltage to current conversion circuitry. the stability of the output current value over temperature is dependent on the stability of the value of r set . as a method of improving the stability of the output current over temperature , an external 15 k ? low drift resistor can be connected to the r set _x pin of the AD5757 to be used instead of the internal resistor , r1. the external resistor is selected via the dac c ontrol register (s ee table 19) . table 1 outlines the performance specifications of the AD5757 with both the internal r set resistor and an external, 15 k? r set resistor. using an external r set resistor allows for improved performance over the internal r set resistor option. the external r set r esistor specification assumes an ideal resistor; the actual performance depends on the absolute va lue and temperature coefficient of the resistor used. this directly affect s the gain error of the output, and thus the total unadjusted error. to arrive at th e gain /tue error of the output with a particular external r set resistor , add the percentage absolute error of the r set resistor directly to the gain /tue error of the AD5757 with the external r set resistor , shown in table 1 (expres sed in % fsr) . hart the AD5757 has four chart pins, one corresponding to each output channels. a hart signal can be coupled into these pins. the hart signal appear s on the corresponding current output, if the output is enable d . ta ble 30 shows the recommended input voltages for the hart signal at the chart pin. if these voltages are used , the current output should meet the hart amplitude specifications. figure 55 shows the recommended circuit for attenuati ng and coupling in the hart signal. table 30 . chart input voltage to hart output current r set chart input voltage current output (hart) internal r set 150 mv p -p 1 ma p -p external r set 170 mv p -p 1 ma p -p hart modem output c1 c2 chartx 09225-076 figure 55 . coupling hart signal a minimum capacitance of c1 + c2 is required to ensure that the 1.2 khz and 2.2 khz hart frequencie s are not significantly
AD5757 data sheet rev. d | page 36 of 44 attenuated at the output. the recommended values are c1 = 22 n f, c 2 = 47 n f. digitally controlling the slew rate of the output is necessary to meet the analog rate of change requirements for hart. dig ital slew r ate c ontrol the s lew r ate c ontrol feature of the AD5757 allows the user to control the rate at which the output value changes. with the slew rat e control feature disabled , the output value change s at a rate limited by the output drive circuitry and the attached load. to reduce the slew rate , this can be achieved by enabling the slew rate control feature. with the feature enabled via the sren bit o f the s lew r ate c ontrol register ( s ee table 25) , the output, instead of slewing directly between two values, step s digitally at a rate defined by two parameters accessible via the s lew r ate c ontrol r egister , as shown in table 25 . the parameters are sr_clock and sr_step. sr_clock defines the rate at which the digital slew is updated, for example, if the selected update rate is 8 k hz , the output update s every 125 s . in conjunc - tion with this , sr_step define s by how much the output value change s at each update. together , both parameters define the rate of change of the output value. table 31 and table 32 outline the range of values for both the sr_clock and sr_step parameters. table 31 . slew rate update clock options sr_clock update clock fr equency (hz) 1 0000 64 k 0001 32 k 0010 16 k 0011 8 k 0100 4 k 0101 2 k 0110 1 k 0111 500 1000 250 1001 125 1010 64 1011 32 1100 16 11 01 8 1110 4 1111 0.5 1 these clock frequencies are divided down from the 13 mhz internal oscillator. see table 1 , figure 46, and figure 47. table 32. slew rate step size options sr_step step size (lsbs) 000 1 001 2 010 4 011 16 100 32 101 64 110 128 111 256 the following equation describes the slew rate as a function of the step size, the update clock frequency , and the lsb size: size lsb frequency clock update size step change output time slew = w here: slew time is expressed in seconds . output change is expressed in a mps for i out _x . when the slew rate control feature is enabled, all output changes occur at the programmed slew rate (see the dc - to - dc converter settl ing time section for additional information ) . for example , if the clear pin is asserted , the output slew s to the clear value at the programmed slew rate (assuming that the c lear channel is enabled to be cleared) . if a number of channels are enabled for sl ew , care must be taken when asserting the clear pin . if one of the channels is slewing when clear is asserted , other channels may change directly to their clear value s not under slew rate control . the update clock frequency for any given value is the same for all output ranges . the step size , however , var ies across output ranges for a given value of step size because the lsb size is different for each output range. power dissipation c ontrol the AD5757 contains integrated dynamic power control using a dc - to - dc boost converter circuit , allowing reductions in power consumption from standard designs. in standard current input module designs , the load resistor values can range from typically 50 ? to 750 ? . output module systems must source enough voltage to meet the compliance voltage requirement across the full range of load resistor values. for example, in a 4 ma to 20 m a loop when driving 20 m a, a compliance voltage of >15 v is required. when driving 20 m a into a 50 ? load , only 1 v compliance is required. t he AD5757 circuitry senses the output voltage and regulates this voltage to meet compliance requirements plus a small headroom voltage. the AD5757 is capable of driving up to 24 ma through a 1 k? load. dc - to - dc converters the AD5757 contains four independe nt dc - to - dc converters. these are used to provide dynamic control of the v boost supply voltage for each channel ( s ee figure 49 ). figure 56 shows the discret e components needed for the dc - to - dc circuitry , and the following sections describe component selection and operation of this circuitry. av cc l dcdc d dcdc c dcdc 4.7f c filter 0.1f r filter c in swx v boost_x ??) ? 10h 09225-077 figure 56 . dc - to- dc circuit
data sheet AD5757 rev. d | page 37 of 44 table 33 . recommended dc -to - dc components symbol component value manufacturer l dcdc xa l4040 - 103 10 h coil c raft ? c dcdc grm32er71h475ka88l 4.7 f murata d dcdc pmeg3010bea 0.38 v f nxp it is recommended to place a 10 ?, 100 nf low - pass rc filter after c dcdc . this consume s a small amount of power but reduce s the amount of ripple on the v boos t _x supply. dc - to - dc converter operation the on - board dc - to - dc converters use a constant frequency, peak curr ent mode control scheme to step up an av cc input of 4.5 v to 5.5 v to drive the AD5757 output channel. these are designed to operate in discontinuo us conduction mode (dcm) with a duty cycle of < 90% typical . discontinuous cond uction mode refers to a mode of operation where the inductor current goes to zero for an appreciable percentage of the switching cycle. the dc - to - dc converters are nonsynchronous ; that is, they requ ire an external schottky diode. dc - to - dc converter output voltage when a channel current output is enabled , the converter regu lates the v boost _x su pply to 7.4 v (5%) or (i out r load + headroom) , whichever is greater (see figure 31 for a plot of headroom supplied vs . output current ) . when the output is disabled, the converter regulates the v boost_x supply to 7.4 v (5%). dc - to - dc converter settling time t he settling time for a step greater than ~1 v (i out r l oad ) is dominated by the settling time of the dc - to - dc converter . the exception to this is when the required voltage at the i out _x pin plus the compliance voltage is below 7.4 v (5%). a typical plot of the output settling time can be found in figure 26 . this plot is for a 1 k? load. the settling time for smaller loads is faster. the settling time for current steps less than 24 ma is also faster. dc - to - dc converter v max functionality the maximum v boost _x voltage is set in the dc - to - dc c ontrol r egister ( 23 v, 2 4.5 v, 27 v , or 2 9.5 v ; s ee table 24 ). on reaching this maximum voltage , the dc - to - dc converter is disabled , and the v boost _x voltage is allowed to decay by ~0.4 v. after the v boost _x voltage has decayed by ~0.4 v , the dc - to - dc converter is re ena bled , and the voltage ramp s up again to v max , if still required. this operation is shown in figure 57. 28.6 28.7 28.8 28.9 29.0 29.1 29.2 29.3 29.4 29.5 29.6 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 v boost voltage (v) time (ms) v max 0ma to 24ma range, 24ma output output unloaded dc-dcmaxv = 29.5v dc_dc bit dc-dcx bit = 0 dc-dcx bit = 1 f sw = 410khz t a = 25c 09225-183 figure 57 . operation on reaching v max as shown in figure 57, the dc - dcx b it in the status register assert s when the AD5757 is ramping to the v max value but deassert s when the voltage is decaying to v max ? ~0.4 v . dc - to - dc converter on - board switch the AD5757 contains a 0.4 25 ? internal switch . the switch current is monit ored on a pulse by pulse basis and is limited to 0.8 a peak current. dc - to - dc converter switching frequency and phase the AD5757 dc - to - dc converter switching frequency can be selected from the dc - to - dc c ontro l r egister. the phasing of the channels can also be adj usted so that the dc - to - dc converter can clock on different edges ( s ee table 24 ). for typical applications , a 410 kh z frequency is recommended. at light loads (low output current and small load resistor) , the dc - to - dc converter en ters a pulse - skipping mode to minimize switching power dissipation. dc - to - dc converter inductor selection for typical 4 ma to 20 ma applications , a 10 h inductor (such as the xal4040 - 103 from coilcraft) , combined with a switch - ing frequency of 410 kh z , al low s up to 24 ma to be driven into a load resistance of up to 1 k? with an av cc supply of 4.5 v to 5.5 v . it is important to ensure that the inductor is able to handle the peak current without saturating , especially at the maximum ambient temperature. if the inductor enter s into saturation mode , it res ult s in a decreas e in efficiency. the inductance value also drop s during saturation and may result in the dc - to - dc converter circuit not being able to supply the required output power. dc - to - dc converter external schottky selection the AD5757 requires an external schottky for correct operation. ensure that the schottky is rated to handle the maximum reverse breakdown expected in operation and that the rectifier maximum junction temperature is not exceeded. the diode average current is approximately equal to the i load curren t. diodes with larger forward voltage drops result in a decrease in efficiency.
AD5757 data sheet rev. d | page 38 of 44 dc - to - dc converter compensation capacitors as the dc - to - dc converter operates in dcm , the uncompensated transfer f unction is essentially a single - pole transfer function. the po le frequency of the transfer function is determined by the dc - to - dc converter s output capacitance, input and output voltage , and output load. the AD5757 uses an external capaci - tor in conjunction with an internal 150 k ? resistor to compensate the regulator loop. alternatively , an external compensation resistor can be used in series with the compensation capacitor by setting the dc - dc comp bit in the dc - to - dc c ontrol r egister. in this case , a ~50 k? resistor is recommend ed . a description of the advantages of this can be found in the ai cc supply requirements slewing section. for typical applications , a 10 nf dc - to - dc compensation capacitor is recommended. dc - to - dc converter input and output capac itor selection the output capacitor a ffects ripple voltage of the dc - to - dc con - verter and indirectly limits the maximum slew rate at which the channel output current can rise. the ripple voltage is caused by a com bination of the capacitance and equivalent series resistance ( esr ) of the capacitor. for the AD5757 , a ceramic capacitor of 4.7 f is recommended for typical applications. larger capacitors or paral lel ed capacitors improve the ripple at t he expense of reduced slew rate . larger capacitors also impa ct the av cc supplies current requirements while slewing (see the ai cc supply requirements slewing section). this capaci t ance at the output of the dc - to - dc converter should be > 3 f under all operating conditions. the input capac itor provide s much of the dynamic current required for the dc - to - dc converter and should be a low esr component. for the AD5757 , a low esr tantalum or ceramic capacitor of 10 f is recommended for typical applications. ceramic capacitors must be chosen car efully because they can exhibit a large sensitivity to dc bias voltages and temperature. x5r or x7r dielectrics are preferred because these capacitors remain stable over wider operating voltage and temperature ranges. care must be taken if selecting a tant alum capacitor to ensure a low esr value. ai cc supply requirements static the dc - to - dc converter is designed to supply a v boost _x voltage of v boost = i out r load + headroom (2) see figure 31 for a plot of headroom supplied vs . o utput voltage . this means that, for a fixed load and output voltage , the dc - to - dc converter output current can be calculated by the following formula: cc v boost out cc cc av v i av efficiency out power ai boost = = (3) w here: i out is the output current from i out_ x in amps. v boost is the efficiency at v boost _x as a fraction (see figure 33 and figure 34) . ai cc supply requirements s lewing the ai cc current requirement while slewing is greater than in static operation because t he output power increases to charge the output capacitance of the dc - to - dc converter. this transient current can be quite large (see figure 58 ), al though the methods described in the reducing ai cc current requirements section can reduce the requirements on the av cc supply. if not enough ai cc current can be provided, the av cc voltage drop s . due to this av cc dro p , the ai cc current required to slew increase s further. this means that the voltage at av cc drop s further (see equation 3) and the v boost _x voltage , and thus the output volt - age , may never reach its intended value. because this av cc voltage is common to all channels, this may also affect other channels. 0 5 10 15 20 25 30 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 0.5 1.0 1.5 2.0 2.5 i out_x current (ma )/ v boost_x vo lt age (v) ai cc current (a) time (ms) ai cc i out v boost 0ma to 24ma range n?/2$' f sw = 410khz inductor = 10h (xal4040-103) t a = 25c 09225-184 figure 58 . ai cc curren t vs. time for 24 ma step through 1 k load with internal compensation resistor reducing ai cc current requirements there are two main methods that can be used to reduce the ai cc current requirements. one method is to add an external compensation resistor , and the other is to use slew rate control. both of these methods can be used in conjunction. a compensation resistor can be placed at the comp dcdc _x pin in series with the 10 nf compensation capacitor. a 51 k? external compensation resistor is recommended. this compensation incre ase s the slew time of the current output but ease s the ai cc transient current requirements. figure 59 shows a plot of ai cc current for a 24 ma step through a 1 k? load when using a 51 k? compensation resistor. this method ease s th e current requirements through smaller loads even further, as shown in figure 60.
data sheet AD5757 rev. d | page 39 of 44 0 4 12 8 16 24 20 28 32 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 ai cc current (a) 0ma to 24ma range 1k? load f sw = 410khz inductor = 10h (xal4040-103) t a = 25c 0 0.5 1.0 1.5 2.0 2.5 i out_x current (ma)/v boost_x voltage (v) time (ms) ai cc i out v boost 09225-185 figure 59. ai cc current vs. time for 24 ma step through 1 k load with external 51 k compensation resistor 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 ai cc current (a) 0ma to 24ma range 500 ? load f sw = 410khz inductor = 10h (xal4040-103) t a = 25c 0 4 12 8 16 24 20 28 32 0 0.5 1.0 1.5 2.0 2.5 i out_x current (ma)/v boost_x voltage (v) time (ms) ai cc i out v boost 09225-186 figure 60. ai cc current vs. time for 24 ma step through 500 load with external 51 k compensation resistor using slew rate control can greatly reduce the av cc supplies cur- rent requirements, as shown in figure 61. when using slew rate control, attention should be paid to the fact that the output cannot slew faster than the dc-to-dc converter. the dc-to-dc converter slews slowest at higher currents through large (for example, 1 k) loads. this slew rate is also dependent on the configuration of the dc-to-dc converter. two examples of the dc-to-dc converters output slew are shown in figure 59 and figure 60 (v boost corre- sponds to the dc-to-dc converters output voltage). 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 ai cc current (a) 0ma to 24ma range 1k ? load f sw = 410khz inductor = 10h (xal4040-103) t a = 25c 0 4 12 8 16 24 20 28 32 01 2345 6 i out_x current (ma)/v boost_x voltage (v) time (ms) ai cc i out v boost 09225-187 figure 61. ai cc current vs. time for 24 ma step through 1 k load with slew rate control external pmos mode the AD5757 can also be used with an external pmos transistor per channel, as shown in figure 62. this mode can be used to limit the on-chip power dissipation of the AD5757, though this will not reduce the power dissipation of the total system. the igate functionality is not typically required when using the dynamic power control feature so figure 62 shows the configura- tion of the device for a fixed v boost_x supply. in this configuration the sw x pin are left floating and the gndsw x pin is grounded. the v boost_x pin is connected to a minimum supply of 7.5 v and a maximum supply of 33 v. this supply can be sized according to the maximum load required to be driven. the igate functionality works by holding the gate of the external pmos transistor at (v boost_x ? 5 v). this means that the majority of the channels power dissipation will take place in this external pmos transistor. the external pmos transistor should be chosen tolerate a v ds voltage of at least ?v boost_x , as well as to handle the power dissipation required. this external pmos transistor typically has minimal effect on the current output performance. 09225-190 r1 r2 r3 r set_a r load swgnd a v boost_a (v boost_a ?5v) sw a charta igatea current output dac channe l a (left floating) i out_a dac a 5.0v a v cc figure 62. configuration off a particular channel using igate
AD5757 data sheet rev. d | page 40 of 44 applications informa tion current output mode w ith internal r set when using the internal r set resistor in current output mode, the output is significantly affected by ho w many other channels using the internal r set are enabled and by the dc crosstalk from these channels. the internal r set specifications in table 1 are for all channels enabled with the internal r set selected and outputting the sa me code. for every channel enabled with the internal r set , the offset error decreases. for example, with one current output enabled using the internal r set , the offset error is 0.075% fsr. this value decreases proportionally as more current channels are en abled; the offset error is 0.056% fsr on each of two channels, 0.029% on each of three channels, and 0.01% on each of four channels. similarly, the dc crosstalk when using the internal r set is propor - tional to the number of current output channels enabled with the internal r set . for example, with the measured channel at 0x8000 and one channel going from zero to full scale, the dc crosstalk is ?0.011% fsr. with two channels going from zero to full scale, it is ?0.019% fsr, and with all three other channels going from zero to full scale, it is ?0.025% fsr. for the full - scale error measurement in table 1 , all channels are at 0xffff. this means that, as any channel goes to zero scale, the full - scale error increases due to the dc crosst alk. for example, with the measured channel at 0xffff and three channels at zero scale, the full - scale error is 0.025%. similarly, if only one channel is enabled in current output mode with the internal r set , the full - scale error is 0.025% fsr + 0.075% fsr = 0.1% fsr. precision voltage re ference selection to achieve the optimum performance from the AD5757 over its full operating temperature range, a precision voltage reference must be used. thought should be given to the selection of a precision voltage ref erence. the voltage applied to the reference inputs is used to provide a buffered reference for the dac cores. therefore, any error in the voltage reference is reflected in the outputs of the device. there are four possible sources of error to consider whe n choosing a voltage reference for high accuracy applications: initial accuracy, temperature coefficient of the output voltage, long - term drift, and output voltage noise. initial accuracy error on the output voltage of an external refer - ence can lead to a full - scale error in the dac. therefore, to minimize these errors, a reference with low initial accuracy error specification is preferred. choosing a reference with an output trim adjustment, such as the adr425 , allows a system designer to trim system errors out by setting the reference voltage to a voltage other than the nominal. the trim adjust - ment can be used at any temperature to trim out any error. long - term drift is a measure of how much the reference outp ut voltage drifts over time. a reference with a tight long - term drift specification ensures that the overall solution remains relatively stable over its entire lifetime. the temperature coefficient of a references output voltage affects inl, dnl, and tue. a reference with a tight temperature coefficient specification should be chosen to reduce the depend - e nce of the dac output voltage to ambient temperature . in high accuracy applications, which have a relatively low noise budget, reference output voltage n oise must be considered. choosing a reference with as low an output noise voltage as practi - cal for the system resolution required is important. precision voltage references such as the adr435 (xfet design) pro duce low output noise in the 0.1 hz to 10 hz region. however, as the circuit bandwidth increases, filtering the output of the reference may be required to minimize the output noise. driving inductive lo ads when driving inductive or poorly defined loads , a capacitor may be required between i out _x and agnd to ensure stability. a 0.01 f capacitor between i out _x and agnd ensures stability of a load of 50 mh. the capacitive component of the load may cause slower settling, although this may be masked by the set - tling time of the AD5757 . there is no maximum capacitance limit for the current output of the AD5757 . table 34 . recommended precision references part no. initial accuracy (mv maximum) long - term drift (ppm typical) temperature dri ft (ppm/c maximum) 0.1 hz to 10 hz noise (v p - p typical) adr445 2 50 3 2.25 adr02 3 50 3 10 adr435 2 40 3 8 adr395 5 50 9 8 ad586 2.5 15 10 4
data sheet AD5757 rev. d | page 41 of 44 transient voltage pr otection the AD5757 contains esd protection diodes that prevent dam - age from normal handling. the industr ial control environment can, however, subject i/o circuits to much higher transients. to protect the AD5757 from excessively high voltage transients, external power diodes and a surge current limiting resistor (r p ) are required, as shown in figure 63 . a typical value for r p is 10 ?. the two protection diodes and the resistor (r p ) must have appro - priate power ratings. r load r d1 d2 p AD5757 v boost_x i out_x agnd c d c d c 4 . 7 f c f i l t e r 0 . 1 f r f i l t e r 1 0 ? (from dc- t o-dc converter) 09225-013 figure 63 . output transient voltage protection additional protection can be provided using transient voltage suppressors (tvss), also referr ed to as transorbs. these compo - nents are available as unidirectional suppressors, which protect against positive high voltage transients, and as bidirectional suppressors, which protect against both positive and negative high voltage transients. transient voltage suppressors are avail - able in a wide range of standoff and breakdown voltage ratings. the tvs should be sized with the lowest breakdown voltage possible while not conducting in the functional range of the current output. it is recommended that all field connected nodes be protected. microprocessor inter facing microprocessor interfacing to the AD5757 is via a serial bus that uses a protocol compatible with microcontrollers and dsp processors. the communications channel is a 3 - wire minimum interface consisting of a clock signal, a data signal, and a latch signal. the AD5757 require s a 24 - bit data - word with data valid on the falling edge of sclk. the dac output update is initiated on either the rising edge of ldac or, if ldac is held low, on the rising edge of sync . the contents of the registers can be read using the readback function. AD5757 - to - adsp - bf527 interface the AD5757 can be connected directly to the sport interface of the ad sp - bf527, an analog devices, inc., blackfin? dsp. figure 64 shows how the sport interface can be connected to control the AD5757 . AD5757 sync sclk sdin ldac sport_tfs sport_tsck sport_dto gpio0 adsp-bf527 09225-080 figure 64 . AD5757 - to - adsp - bf527 sport interface layout guidelines groundi ng in any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the AD5757 is mounted should be designed so that the analog and digi tal sections are separated and confined to certain areas of the board. if the AD5757 is in a system where multiple devices require an agnd - to - dgnd connection, the connection should be made at one point only. the star ground point should be established as c lose as possible to the device. the gndsw x and ground connection for the av cc supply are referred to as pgnd. pgnd should be confined to certain areas of the board, and the p gnd - to - agnd connection should be made at one point only. supply dec oupling the ad5 757 should have ample supply bypassing of 10 f in parallel with 0.1 f on each supply located as close to the package as possible, ideally right up against the device. the 10 f capacitors are the tantalum bead type. the 0.1 f capaci - tor should have low effective series resistance (esr) and low effective series inductance (esl ) , such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. traces the power supply lines of the AD5757 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals such as clocks should be shielded with digital ground to prevent radiatin g noise to other parts of the board and should never be run near the reference inputs. a ground line routed between the sdin and sclk lines helps reduce crosstalk between them (not required on a multilayer board that has a separate ground plane, but separa ting the lines helps). it is essential to minimize noise on the refin line because it couples through to the dac output. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this red uces the effects of feedthrough on the board. a microstr ip technique is by far the best but not always possible with a double - sided board. in this technique, the component side of the board is dedicated to ground plane, whereas signal traces are placed on the solder side.
AD5757 data sheet rev. d | page 42 of 44 dc - to - dc converters to achieve high efficiency, good regulation, and stability, a well - designed printed circuit board layout is required. follow these guidelines when designing printed circuit boards ( s ee figure 56 ): ? keep the low esr input capacitor, c in , close to av cc and p gnd. ? keep the high current path from c in through the inductor, l dcdc , to sw x and pgnd as short as possible. ? keep the high current path from c in through l dcdc and the rectifier, d dcdc , to the output capacitor, c dcdc , as short as possible. ? keep high current traces as short and as wide as possible. the path from c in through the inductor, l dcdc , to sw x and pgnd should be able to handle a minimum of 1 a. ? place the compensation components as close as possible to comp dcdc _x . ? avoid routing high impedance traces near any node connected to sw x or near the inductor to prevent radiated noise injection. galvanically isolate d interface in many process control applications, it is necessary to provide an i solation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common - mode voltages that may occur. analog devices i coupler? products can provide voltage isolation in excess of 2.5 kv. the serial loading structure of the AD5757 makes it ideal for isolated interfaces because the number of interface lines is kept to a minimum. figure 65 shows a 4 - channel isolated interface to the AD5757 using an adum1400 . for more information, visit www.analog.com . v ia serial clock out to sclk v oa encode decode v ib serial data out to sdin v ob encode decode v ic sync out v oc encode decode v id control out v od encode decode microcontroller adum1400 additional pins omitted for clarity. to sync to ldac 09225-081 figure 65 . isolated interface
data sheet AD5757 rev. d | page 43 of 44 i ndustrial hart c apable a nalog o utput a pplication many industrial control applications have requirements for accurately controlled current output signals, and the AD5757 is ideal for such applications. figure 67 shows the AD5757 in a circuit design for a hart - enabled output module, spec ifically for use in an industrial control application. the design provides for a hart - enabled current output, with the hart capability provided by the ad5700/ad5700 - 1 hart m odem, the industrys lowest power and smallest footprint hart - compliant ic modem. for additional space - savings, the ad5700 - 1 offers a 0.5% precision internal oscillator. the hart_out signal from the ad5700 is attenuated and ac - coupled into the chart x pin of the AD5757. such a configuration results in the ad5700 hart modem output modulat ing the 4 ma to 20 ma analog current without affecting the dc level of the current. this circuit adheres to the hart physical layer specifications as defined by the hart communication foundation. for transient overvoltage protection, a 24 v transient volt age sup - pres sor (tvs) is placed on the i out /v out connection. for added protection, clamping diodes are connected from the i out _x /v out _x pi n to the av dd and gnd power supply pins. a 5 k current limiting resistor is also placed in series with the +vsense_x input. this is to limit the current to an acceptable level during a transient event. the recommended external band - pass filter for the ad5700 hart modem includes a 150 k resistor, which limits current to a sufficiently low level to adhere to intrinsic saf ety requirements. in this case, the input has higher transient voltage protection and should, therefore, not require additional protection circuitry, even in the most demanding of industrial environments. AD5757 09225-065 mcu uart interface 10f 10k? 10f 0.1f 0.1f 0.1f 0.1f 2.7v to 5.5v dv dd av dd reset alert fault clear sync ldac sclk sdin sdo dgnd ad5700/ad5700-1 txd v cc rxd rts cd hart_out 15v av cc 5v sw(x4) v boost (x4) iout b,c,d chart b,c,d iouta d2 d1 d3 r p r l refout refin chart a gnd 22nf c1 47nf c2 4.20ma currentloop adc_ip ref gnd 1f 150k? 150pf 300pf 1.2mq 1.2mq figure 66 . AD5757 in hart configuration
AD5757 data sheet rev. d | page 44 of 44 outline dimensions compliant to jedec standards mo-220-vmmd-4 0.25 min 1 64 16 17 49 48 32 33 0.50 0.40 0.30 0.50 bsc 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 7.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max seating plane pin 1 indicator 7.25 7.10 sq 6.95 pin 1 indicator 0.30 0.23 0.18 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. top view exposed pad bottom view 9.10 9.00 sq 8.90 8.85 8.75 sq 8.65 06-13-2012-c figure 67. 64- lead lead frame chip scale package [lfcsp_vq] 9 mm 9 mm body, very thin quad (cp-64-3) dimensions shown in millimeters ordering guide model 1 resolution (bits) temperature range package description package option AD5757acpz 16 ?40c to +105c 64-lead lead frame chip scale package [lfcsp_vq] cp-64-3 AD5757acpz-reel7 16 ?40c to +105c 64-lead lead frame chip scale package [lfcsp_vq] cp-64-3 eval-AD5757sdz evaluation board 1 z = rohs compliant part. ?2011C2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d09225-0-11/12(d)

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